1. Field of the Invention
The present invention relates to an image sensor, particularly an image sensor such as a CCD (charge coupled device) image sensor having a reset transistor.
2. Description of Related Art
In accordance with diffusion of digital cameras and mobile phones with cameras, CCD image sensors have been distributed to the market. The CCD image sensor, which is disclosed in Japanese Laid-Open Patent Application JP-A-Heisei 1-196175, is provided with a light-receiving element, a CCD, and a FDA (floating diffusion amplifier). The light-receiving element converts or photoelectrically converts light into signal charges and accumulates the signal charges. The CCD transfers the signal charges accumulated in the light-receiving element into the FDA. The FDA detects the transferred signal charges and converts them into an electric signal or a voltage.
On the basis of an amount of transferred signal charges, the FDA converts the charge amount into a voltage. The FDA is provided with a reset transistor in a rear stage thereof. The reset transistor is provided with a reset gate and a reset drain. The reset transistor provides the reset drain with the charges converted to the voltage by the FDA. Therefore, in the CCD image sensor, it is prevented to mix charges that were already detected by the FDA, and charges to be detected.
FIG. 1 is a sectional view showing a constitution of the above-mentioned CCD image sensor 11 disclosed in the Japanese Laid-Open Patent Application JP-A-Heisei 1-196175. The disclosed CCD image sensor 11 is provided with a CCD register transfer electrode portion 13 and a floating diffusion 15. The CCD register transfer electrode portion 13 is formed on a P substrate 12. The floating diffusion 15 converts charges transferred from the CCD register transfer electrode 13 into a signal voltage, and is formed on the P substrate 12. The CCD image sensor 11 also has a reset transistor composed by the floating diffusion 15, a reset gate electrode 16, and a reset drain 17. The reset transistor resets a potential of the floating diffusion 15 to a reference potential at a predetermined timing.
Referring to FIG. 1, an output gate electrode 14 is provided between the CCD register transfer electrode portion 13 and the floating diffusion 15. The output gate electrode 14 provides the transferred charges for the floating diffusion 15 at a predetermined timing. The floating diffusion 15 is further connected to an output amplifier 18, and the floating diffusion 15 converts transferred charges into a signal voltage which is provided for the output amplifier 18. The output amplifier 18 amplifies the signal voltage to output from an output node Vout.
A reset pulse ΦR is applied to the reset gate electrode 16 of which the reset transistor is composed. The CCD register transfer electrode portion 13 is provided with a first transfer electrode and a second transfer electrode. The first transfer electrode is operated in response to a first clock Φ1. The second transfer electrode is operated in response to a second clock Φ2. As shown in FIG. 1, an N diffusion region and an N− diffusion region that are formed in the P substrate 12 are provided in a lower part of the first transfer electrode. Therefore, the N diffusion region of the first transfer electrode acts as a storage electrode with the potential that is made deeper in response to the first clock Φ1. The N− diffusion region of the first transfer electrode acts as a barrier electrode with the potential that is made shallower in response to the first clock Φ1.
That is, the first transfer electrode includes a pair of the storage electrode and the barrier electrode. Similarly, the second transfer electrode includes a pair of a storage electrode with the potential thereunder that is made deeper, and a barrier electrode with the potential thereunder that is made shallower, in response to the second clock Φ2. As shown in FIG. 1, an N− diffusion region is formed in a lower part of the output gate electrode 14 in the P substrate 12. An output gate voltage VOG is applied to the output gate electrode 14.
An operation timing of the disclosed CCD image sensor 11 will be explained below referring to a drawing. FIGS. 2A to 2D are timing charts showing an operation of the disclosed CCD image sensor 11. A waveform shown in FIG. 2A indicates the first clock 11. A waveform shown in FIG. 2B indicates the second clock Φ2. A waveform shown in FIG. 2C indicates the reset pulse ΦR. A waveform shown in FIG. 2D indicates a signal voltage from the output node Vout.
Referring to FIGS. 2A to 2D, the first clock Φ1 exhibits a low level and the second clock Φ2 exhibits a high level at time t11. At time t12, the first clock Φ1 is brought into the high level, and the second clock Φ2 is brought into the low level. At this time, the reset pulse ΦR maintains the low level. At time t13, the reset pulse ΦR is inverted from the low level to the high level. At this time, the first clock Φ1 and the second clock Φ2 are also inverted. The reset pulse ΦR maintains the high level from time t13 through time t14 up to time t15. At time t15, the reset pulse ΦR is inverted from the high level to the low level. Furthermore, at time t16, the reset pulse ΦR is brought into the same state as that of time 11.
A charge transfer at the above-mentioned operation timing will be explained below referring to a drawing. FIGS. 3A to 3D are views showing changes and potentials in the disclosed CCD image sensor 11. FIGS. 3A to 3D show situations in which charges are transferred by changing a potential depth in response to a voltage applied to each of the electrodes in the CCD image sensor 11. Referring to FIGS. 3A to 3D, in the disclosed CCD image sensor 11, a potential from the first transfer electrode to the second transfer electrode becomes a stepwise state at time t11. At this time, the output gate voltage VOG is set such that the output gate electrode 14 becomes a barrier. Therefore, signal charges es1 are accumulated in the storage electrode of the second transfer electrode. At time t11, the reset pulse ΦR in the low level is applied to the reset gate electrode 16. Therefore, an N type diffusion region disposed between the floating diffusion 15 and the reset drain 17 in a lower part of the reset gate electrode 16 becomes a potential barrier to separate both of the floating diffusion 15 and the reset drain 17.
At time 12, the first clock Φ1 and the second clock Φ2 are inverted. Accordingly, signal charges es2 obtained from a transfer electrode in the previous stage (not shown) are transferred to the storage electrode of the first transfer electrode. At this time, the charges es1 which were transferred to the storage electrode of the second transfer electrode are transferred to the floating diffusion 15. The floating diffusion 15 responds to the transferred charges and converts an amount of the charges into a signal voltage which is outputted to the output amplifier 18.
At time t13, the reset pulse ΦR in the high level is applied to the reset gate electrode 16. Therefore, the potential under the reset gate electrode 16 is made deeper than the potential under the floating diffusion 15. Thereafter, at time t14, the reset gate electrode 16 stops to act as the potential barrier, so that the charges in the floating diffusion 15 is outputted to the reset drain 17.
Next, at time t15, the reset pulse ΦR is brought into the low level. At this time, the potential under the reset gate electrode 16 is decreased. The reset transistor is turned off by the reset pulse ΦR that is brought into the low level. At this time, the charges that existed in the N type diffusion region under the reset gate electrode 16 at time t14 is distributed to both directions of the floating diffusion 15 and the reset drain 17.
If the floating diffusion 15 is in a floating state, the distributed charges er1 or charges er2 are made to be a reset feed-through noise (hereinafter, referred to as a reset noise). The reset noise shifts the potential of the floating diffusion 15 to a low potential. Referring to FIG. 2D, the potential of the output node Vout at time t16 is shifted from a VRD level to a reset feed-through level VF1.
In the disclosed CCD image sensor 11, a reset feed-through noise which is a difference between the VRD level and the reset feed-through level VF1 is outputted as a reset noise VRF1. The reset noise VRF1 occasionally causes a demerit such as deteriorating a pixel signal and narrowing a dynamic range of an amplifier circuit. Therefore, there is known a technique to reduce a reset noise.
Japanese Laid-Open Patent Application JP-A-Heisei 6-205309 discloses the technique to reduce the reset noise. FIG. 4 is a sectional view showing a constitution of a CCD image sensor 23 described in the Japanese Laid-Open Patent Application JP-A-Heisei 6-205309. The CCD image sensor 23 is provided with a reset gate electrode 20 between the floating diffusion 15 and the reset drain 17. Referring to FIG. 4, the reset gate electrode 20 includes a first reset gate electrode 21 and a second reset gate electrode 22. As shown in FIG. 4, the reset pulse ΦR is applied to the first reset gate electrode 21. The second reset gate electrode 22 is connected to a resistance R101, and the reset pulse ΦR is applied via the resistance R101. Expect for this constitution, the CCD image sensor 23 is the same as the above-mentioned CCD image sensor 11.
FIGS. 5A to 5E are timing charts showing an operation of the CCD image sensor 23. FIG. 5A exhibits a waveform of the first clock Φ1. FIG. 5B exhibits a waveform of the second clock Φ2. FIG. 5C exhibits a waveform of the reset pulse ΦR applied to the first reset gate electrode 21. FIG. 5D exhibits a waveform of a reset pulse ΦR′ applied to the second reset gate electrode 22 via the resistance R101. FIG. 5E exhibits a waveform of a signal voltage outputted from the output node Vout.
Referring to FIGS. 5A to 5E, the first clock Φ1 becomes the low level and the second clock Φ2 becomes the high level at time t21. At time t22, the first clock Φ1 is brought into the high level, and the second clock Φ2 is brought into the low level. At this time, the reset pulse ΦR maintains the low level. At time t23, the reset pulse ΦR is inverted from the low level to the high level. At this time, the first clock Φ1 and the second clock Φ2 are also inverted. The reset pulse ΦR maintains the high level from time t23 through time t24 up to time t25.
As mentioned above, the resistance R101 is interposed between the second reset gate electrode 22 and a node N01. Therefore, waveform dullness caused by an RC delay due to the resistance R 101 and a gate capacity is observed in a pulse waveform of the delay reset pulse ΦR′ supplied to the second reset gate electrode 22. At time t24, the delay reset ΦR′ is brought into the high level. The delay reset pulse ΦR′ is shifted from the low level to the high level in a period from time t23 to time t24. At time t25, the reset pulse ΦR is inverted from the high level to the low level. Furthermore, at time t26, the delay reset pulse ΦR′ is brought into the low level. Here, each of the elements is brought into a state similar to that of time t21.
FIGS. 6A to 6F are views showing charges and potentials of the CCD image sensor 23. Referring to FIGS. 6A to 6F, at time t21, the signal charges es1 are accumulated in the storage electrode of the second transfer electrode due to the output gate electrode 14 which becomes a barrier. At this time, the reset pulse ΦR becomes the low level, so that the reset gate electrode 20 existing between the floating diffusion 15 and the reset drain 17 becomes a potential barrier which separates both of the floating diffusion 15 and the reset drain 17.
At time t22, the first clock Φ1 and the second clock Φ2 are inverted. Therefore, the signal charges es2 are transferred form a transfer electrode (not shown) in the previous stage to the storage electrode of the first transfer electrode. The charges es1 accumulated in the storage electrode of the second transfer electrode are transferred to the floating diffusion 15. The floating diffusion 15 outputs a signal voltage to the output amplifier 18 in response to an amount of the charges.
At time t23, the reset pulse ΦR is brought into the high level. The reset pulse ΦR is directly applied to the first reset gate electrode 21 here. Accordingly, at time t23, the potential of the N type diffusion region under the first reset gate electrode 21 is made deeper than that of the floating diffusion 15. Next, at time t24, the potential of an N type diffusion region under the second reset gate electrode 22 is made deeper than that of the floating diffusion 15. Therefore, at time t24, a potential barrier between the floating diffusion 15 and the reset drain 17 is removed, so that charges in the floating diffusion 15 (charges es1+charges er1) are reset to the reset drain 17.
Next, at time t25, the reset pulse ΦR is brought into the low level. The potential of the N type diffusion region under the first reset gate electrode 21 rises in response to the reset pulse ΦR. The delay reset pulse ΦR′ supplied to the second reset gate electrode 22 is delayed by an action of the resistance R101. The potential of the N type diffusion region under the second reset gate electrode 22 rises at time t26. At this time or in a time period between time t25 and time t26, the reset gate electrode 20 has a temporary reset gate potential which is stepwise and deeper toward the side of the reset drain 17. Accordingly, charges in the side of the second reset gate electrode 22 are entirely transferred to the reset drain 17, and the distributed charges er2 on the side of the first reset gate electrode 21 are exclusively distributed and transferred to the floating diffusion 15 and the reset drain 17. Therefore, if a gate length of the reset gate electrode 16 in the CCD image sensor 11 is equal to a gate length of the reset gate electrode 20 in the CCD image sensor 23, for example, an amount of the charges er distributed to the floating diffusion 15 are decreased in the reset gate electrode 20 by charges on the side of the second reset gate electrode 22.
FIG. 7 is a waveform view showing comparison of output voltages of the output node Vout in the above-mentioned cases. A waveform 31 shown in a dotted line indicates an output voltage of the output node Vout in the CCD image sensor 11. A waveform 32 shown in a solid line also indicates an output voltage of the output node Vout in the CCD image sensor 23. It is assumed here that a noise amount of the CCD image sensor 11 is a voltage ΔVRF1, and a noise amount of the CCD image sensor 23 is a voltage ΔVRF2. Referring to FIG. 7, a reset noise in the CCD image sensor 23 is decreased more than that of the CCD image sensor 11.
In conjunction with the above-mentioned techniques, other techniques are disclosed. Japanese Patent 2578615 discloses a technique to form a three-stage concentration gradient in a channel region of a reset transistor in order to distribute charges within the channel region. Japanese Laid-Open Patent Application JP-A-Heisei 11-150685 (corresponding to U.S. Pat. No. 6,570,618B1) discloses a technique to change operation timing of a reset pulse applied to two reset gates. Japanese Laid-Open Patent Application JP2005-317993 discloses a technique to configure a stepwise potential which is made deeper toward a floating diffusion side in a reset gate having two electrodes in order to change charge detection sensitivity.
I have now discovered that the facts which will be described below. In the disclosed CCD image sensor 11, the reset noise charge er2 is distributed to the floating diffusion 15 as mentioned above. Therefore, a charge amount which can be accumulated in the floating diffusion 15 or an accumulation amount of the es is occasionally decreased due to the reset noise charge er2 in the disclosed CCD image sensor 11. Amplitude of a signal voltage is also increased by the reset noise charge er2 in the disclosed CCD image sensor 11. Therefore, there are cases of decreasing a dynamic range of an amplifier circuit and causing S/N deterioration. Accordingly, the reset noise charge er2 causes a problem of deteriorating image quality of a read image in the disclosed CCD image sensor 11.
Furthermore, in the disclosed CCD image sensor 11, a waveform of a signal voltage outputted from the output node Vout settles in a level from the VRD to VF when the reset transistor is turned off. At this time, the disclosed CCD image sensor 11 requires prolonged time in a delay to distribute and transfer charges on the gate. Therefore, a period to maintain a VF1 level or a stable level in a signal voltage becomes shorter by a charge transfer delay. In a signal output of the CCD, a signal level is captured by using the VF1 level as a reference level. Therefore, if a period to maintain the VF1 level or a stable level becomes short, it causes reduction of an operation speed of the CCD.
In order to decrease a reset noise, there is known the CCD image sensor 23 as shown in FIG. 4. The CCD image sensor 23 is provided with a resistance in wiring connected to the second reset gate electrode 22 of the reset gate electrode 20. Accordingly, a period of reset time itself is extended in the reset gate electrode 20 due to pulse deterioration caused by the RC delay. A period before settling in a VF2 level is also extended by a delay period in the CCD image sensor 23. Therefore, there is a problem of decreasing an operation speed even if a reset noise level can be decreased.